Illustrative · unadmitted · revision 1
3-D coincidence-addressed tensor FPGA
This is a proposed definition for criticism. It is not an experiment run, result, evidence claim, canonical admission, inventory record, or procurement request.
- Stable identifier
three-dimensional-coincidence-addressed-tensor-fpga- Kind
- simulation
- Intent
- replication
Exact target
- external-reference ·
three-dimensional-coincidence-addressed-tensor-fpga — operator-supplied 3-D coincidence-addressed tensor FPGA proposal
Minimal decisive protocol
Exact coincidence address oracle
Generate a finite tensor workload, route operands through the declared 3-D coincidence address, and compare FPGA outputs and resource traces with an exact software oracle and a randomized address control.
- Generate deterministic tensor and address fixtures.
- Run exact software oracle.
- Run FPGA design with collision and address logs.
- Compare output tensors, missed coincidences, and resource counters.
Decision rule: The architecture survives only if output and address semantics match the oracle and randomized-address control fails as predicted.
Controls
- randomized: Randomize addresses without changing operand multiset. (coincidence address; Output should change only according to the exact address oracle.)
- positive: Run the exact software reference. (execution substrate; Software output defines the declared comparison target.)
Observables and units
Observables| Observable | Units | Measurement | Uncertainty reporting |
|---|
| tensor output error | integer exact | bitwise comparison to oracle | none for exact integer output; report hardware nondeterminism separately |
|---|
| coincidence collision rate | fraction | address-event log | report counter width and dropped events |
|---|
Calibration and repetitions
- clock and event timestamp: hardware/software timestamp loopback — cycle offset known and stable (cycle)
Replicate unit: deterministic tensor workload; minimum 50, independent 10.
Randomization: seeded workload and address permutations
Stopping rule: complete fixed seed set
Uncertainty: clock counter overflow, event drops, simulator/hardware scheduling; exact mismatch classification rather than statistical averaging; retain bitstreams, seeds, logs, and oracle source hash
Success and falsifiers
Success
- FPGA tensor outputs and address events match the exact oracle for all declared seeds. (mismatching elements = 0 elements)
Falsifiers
- A declared coincidence address produces a dropped, duplicated, or order-dependent tensor contribution. (address semantic mismatch > 0 events)
Confounds and raw artifacts
- counter width hides dropped events: overflow sentinel and software count; mitigation: widen counters and include overflow artifact
- bitstream-and-event-log · verilog/VHDL, binary log, oracle JSON · retain source, tool version, bitstream, and exact seeds
Nonclaims
- This fixture does not claim a fabricated FPGA implementation or benchmark result.
- Exact simulated behavior does not establish physical tensor hardware performance.
Provenance boundary
The citation supplies FPGA tooling context only; it does not support the proposed tensor address semantics or benchmark.
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