{"experiment_id":"three-dimensional-coincidence-addressed-tensor-fpga","revision":1,"title":"3-D coincidence-addressed tensor FPGA","experiment_kind":"simulation","intent":"replication","status":"illustrative-unadmitted","targets":[{"target_id":"three-dimensional-coincidence-addressed-tensor-fpga","target_kind":"external-reference","target_revision":null,"target_label":"operator-supplied 3-D coincidence-addressed tensor FPGA proposal"}],"protocols":[{"protocol_id":"tensor-fpga-minimal-protocol","name":"Exact coincidence address oracle","minimal_decisive_test":"Generate a finite tensor workload, route operands through the declared 3-D coincidence address, and compare FPGA outputs and resource traces with an exact software oracle and a randomized address control.","steps":["Generate deterministic tensor and address fixtures.","Run exact software oracle.","Run FPGA design with collision and address logs.","Compare output tensors, missed coincidences, and resource counters."],"decision_rule":"The architecture survives only if output and address semantics match the oracle and randomized-address control fails as predicted."}],"controls":[{"control_id":"tensor-fpga-random-address","control_kind":"randomized","description":"Randomize addresses without changing operand multiset.","controlled_variable":"coincidence address","expected_relation":"Output should change only according to the exact address oracle."},{"control_id":"tensor-fpga-software","control_kind":"positive","description":"Run the exact software reference.","controlled_variable":"execution substrate","expected_relation":"Software output defines the declared comparison target."}],"observables":[{"observable_id":"tensor-fpga-output-error","name":"tensor output error","units":"integer exact","measurement":"bitwise comparison to oracle","aggregation":"per tensor element","uncertainty_reporting":"none for exact integer output; report hardware nondeterminism separately"},{"observable_id":"tensor-fpga-collision-rate","name":"coincidence collision rate","units":"fraction","measurement":"address-event log","aggregation":"per workload","uncertainty_reporting":"report counter width and dropped events"}],"calibration":[{"calibration_id":"tensor-fpga-clock","quantity":"clock and event timestamp","units":"cycle","method":"hardware/software timestamp loopback","acceptance":"cycle offset known and stable"}],"repetitions":{"replicate_unit":"deterministic tensor workload","minimum_repetitions":50,"independent_repetitions":10,"randomization":"seeded workload and address permutations","stopping_rule":"complete fixed seed set"},"uncertainty":{"sources":"clock counter overflow, event drops, simulator/hardware scheduling","propagation":"exact mismatch classification rather than statistical averaging","reporting":"retain bitstreams, seeds, logs, and oracle source hash"},"success_criteria":[{"criterion_id":"tensor-fpga-success-exact","statement":"FPGA tensor outputs and address events match the exact oracle for all declared seeds.","metric":"mismatching elements","comparator":"=","threshold_text":"0","units":"elements"}],"falsifiers":[{"criterion_id":"tensor-fpga-falsifier-collision","statement":"A declared coincidence address produces a dropped, duplicated, or order-dependent tensor contribution.","metric":"address semantic mismatch","comparator":">","threshold_text":"0","units":"events"}],"confounds":[{"confound_id":"tensor-fpga-counter-overflow","confound":"counter width hides dropped events","detection_control":"overflow sentinel and software count","mitigation":"widen counters and include overflow artifact"}],"raw_artifacts":[{"raw_artifact_id":"tensor-fpga-bitstream-log","artifact_kind":"bitstream-and-event-log","format":"verilog/VHDL, binary log, oracle JSON","retention":"retain source, tool version, bitstream, and exact seeds"}],"nonclaims":["This fixture does not claim a fabricated FPGA implementation or benchmark result.","Exact simulated behavior does not establish physical tensor hardware performance."],"equipment_requirements":[{"requirement_id":"tensor-fpga-board","group_id":"fpga","group_order":1,"group_kind":"required","selection_rule":"any-one","quantity":1,"capability":"FPGA with deterministic cycle/event trace","units":"board","specification":"3-D address logic and raw event counters","equipment_type_ids":["coincidence-addressed-tensor-fpga"]}],"dependencies":[],"relations":[],"topic_links":[{"link_id":"tensor-fpga-topic-link","topic_version_id":"illustrative-minimal-conservative-formal-fragment@1","relation_kind":"candidate-protocol","rationale":"The bounded tensor address and exact comparison are a formal-fragment implementation prompt, not a result."}],"provenance":{"citation_availability":"available","citations":[{"source_id":"amd-fpga-context","label":"AMD FPGA acceleration documentation","url":"https://docs.amd.com/r/en-US/ug1186-fpga-acceleration"}],"boundary":"The citation supplies FPGA tooling context only; it does not support the proposed tensor address semantics or benchmark."},"authority":"illustrative-unadmitted-fixture","source_fixture":"cintamani.illustrative-proposed-experiments.v1","canonical_admission":false,"public_d1_seed":false,"evidence_claim":false,"equipment_types":[{"equipment_type_id":"coincidence-addressed-tensor-fpga","revision":1,"title":"Deterministic coincidence-addressed tensor FPGA","description":"A capability type for finite 3-D coincidence address logic with cycle-accurate event logs.","capabilities":[{"capability_id":"tensor-3d-address","capability":"3-D coincidence address routing","units":"events/cycle","specification":"declared address width and collision semantics"},{"capability_id":"tensor-event-trace","capability":"deterministic raw event trace","units":"cycle","specification":"overflow-safe counters and bitstream hash"}],"operating_limits":[{"operating_limit_id":"tensor-clock","parameter":"clock frequency","lower_bound":"declared","upper_bound":"declared","units":"MHz","notes":"Report timing closure and counter width."}],"calibrations":[{"equipment_calibration_id":"tensor-loopback","quantity":"cycle offset","units":"cycle","method":"software/hardware loopback","traceability":"retain bitstream and toolchain"}],"safety_requirements":[{"safety_requirement_id":"tensor-board-power","hazard":"board power and thermal load","requirement":"current and temperature monitor","mitigation":"thermal shutdown"}],"interface_requirements":[{"interface_requirement_id":"tensor-seed-interface","interface_kind":"data","specification":"deterministic workload seed and exact event log","units":"record"}],"nonclaims":["This type does not imply a deployed FPGA or tensor benchmark."],"citations":[{"source_id":"amd-fpga-context","label":"AMD FPGA acceleration documentation","url":"https://docs.amd.com/r/en-US/ug1186-fpga-acceleration"}]}]}